To simplify the design of the memory circuits, the memory has been divided up into 2 equal parts.
32k of ROM memory. This is probably overkill, but it does make the design a little easier to wire up.
The current design is to use a AT28C256 EEPROM IC.
32k of RAM.
The current design is to use a CY62256NLL-70PXC RAM IC but any similar memory IC should be ok to use.
Since we have split the memory map into two equal parts, we can use the A15 address line to determine which memory chip to enable. This signal is gated by the /MREQ signal.