The System core contains the essential modules required for the operation of the Whiz80. Missing modules will prevent the Whizz80 computer from operating. This core connects to the submodules by a system bus.
The System bus consists of 35 lines. 16-bit Address line (A0-A15), 8-bit Data line (D0-D7), Power (+5v, GND) and 9 control lines (/CLOCK, /RESET, /MEMREQ, /IORQ, /RD, /WR, /INT, /M1/ /WAIT)
Each module connects to the system bus. The following 6 modules make up the system core (5 standard, and 1 special)
The power module supplies regulated power to the whole whizz80 system. Output of this module is via the system bus, and currently consists of +5v, ground and any reset signals.
Outputs a clock signal to the system bus that controls the timing of everything. A simple version of this module might just be an oscillator or a 555 timer, or it could be as complicated as a stepper single shot timer. As long as the output can generate a clean square wave.
I am artificially capping the maximum speed that I intend to build the whizz80 to 2MHz as the faster you make the signals, the more important it becomes with the length of your wires between ICs and other forms of interference. I'm not interested in fast clock speeds.
Contains the Z80 CPU and all the connections to the system bus. A LED is also present to show when the CPU has been halted (usually via the HALT command).
Connects the ROM chip to the system bus. Current design is for a 32Kb of ROM memory. This module is also designed so that it can interface with a custom built EEPROM programmer without removing the chip from the IC socket.
Connects the RAM chip to the system bus. 32Kb of RAM is currently planned.
Connects the system bus to the I/O core bus by decoding the signals from the Z80 CPU.
The System Core concept may look very similar to the RC2014 computer, because when I was initially designing the system core I came across the RC2014. I was so impressed by it that I adapted some of the ideas into my design.